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Found 13 papers, 1 papers with code
Improving DNN Fault Tolerance using Weight Pruning and Differential Crossbar Mapping for ReRAM-based Edge AI
More importantly, our method does not require extra hardware cost compared to the traditional two-column mapping scheme.
CSAFL: A Clustered Semi-Asynchronous Federated Learning Framework
Asynchronous FL has a natural advantage in mitigating the straggler effect, but there are threats of model quality degradation and server crash.
FedSAE: A Novel Self-Adaptive Federated Learning Framework in Heterogeneous Systems
In our framework, the server evaluates devices' value of training based on their training loss.
DARB: A Density-Aware Regular-Block Pruning for Deep Neural Networks
As a further optimization, we propose a density-adaptive regular-block (DARB) pruning that outperforms prior structured pruning work with high pruning ratio and decoding efficiency.
A Stochastic-Computing based Deep Learning Framework using Adiabatic Quantum-Flux-Parametron SuperconductingTechnology
Further, the application of SC has been investigated in DNNs in prior work, and the suitability has been illustrated as SC is more compatible with approximate computations.
ADMM-NN: An Algorithm-Hardware Co-Design Framework of DNNs Using Alternating Direction Method of Multipliers
The first part of ADMM-NN is a systematic, joint framework of DNN weight pruning and quantization using ADMM.
Towards Budget-Driven Hardware Optimization for Deep Convolutional Neural Networks using Stochastic Computing
Recently, Deep Convolutional Neural Network (DCNN) has achieved tremendous success in many machine learning applications.
Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs
For FPGA implementations on deep convolutional neural networks (DCNNs), we achieve at least 152X and 72X improvement in performance and energy efficiency, respectively using the SWM-based framework, compared with the baseline of IBM TrueNorth processor under same accuracy constraints using the data set of MNIST, SVHN, and CIFAR-10.
An Area and Energy Efficient Design of Domain-Wall Memory-Based Deep Convolutional Neural Networks using Stochastic Computing
However, in these works, the memory design optimization is neglected for weight storage, which will inevitably result in large hardware cost.
VIBNN: Hardware Acceleration of Bayesian Neural Networks
In this paper, we propose VIBNN, an FPGA-based hardware accelerator design for variational inference on BNNs.
Deep Reinforcement Learning: Framework, Applications, and Embedded Implementations
The recent breakthroughs of deep reinforcement learning (DRL) technique in Alpha Go and playing Atari have set a good example in handling large state and actions spaces of complicated control problems.
Hardware-Driven Nonlinear Activation for Stochastic Computing Based Deep Convolutional Neural Networks
Recently, Deep Convolutional Neural Networks (DCNNs) have made unprecedented progress, achieving the accuracy close to, or even better than human-level perception in various tasks.
SC-DCNN: Highly-Scalable Deep Convolutional Neural Network using Stochastic Computing
Stochastic Computing (SC), which uses bit-stream to represent a number within [-1, 1] by counting the number of ones in the bit-stream, has a high potential for implementing DCNNs with high scalability and ultra-low hardware footprint.
