Search Results for author:
Found 12 papers, 3 papers with code
Compute-in-Memory based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections
In this study, we define the problem of pinpointing the worst-case performance of CiM DNN accelerators affected by device variations.
U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators
In our research, we illustrate that only a small fraction of weights need this write-verify treatment for the corresponding devices and the DNN accuracy can be preserved, yielding a notable programming acceleration.
Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators through Training with Right-Censored Gaussian Noise
In this work, we propose to use the k-th percentile performance (KPP) to capture the realistic worst-case performance of DNN models executing on CiM accelerators.
On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators
In this study, we present a novel approach that leverages Large Language Models (LLMs) to address this issue.
Negative Feedback Training: A Novel Concept to Improve Robustness of NVCIM DNN Accelerators
However, the stochastic nature and intrinsic variations of NVM devices often result in performance degradation in DNN inference.
ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference
Compared to CPU-based approximate multiplier simulations in training and inference, the GPU-accelerated ApproxTrain is more than 2500x faster.
Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?
In this work, we formulate the problem of determining the worst-case performance of CiM DNN accelerators under the impact of device variations.
SWIM: Selective Write-Verify for Computing-in-Memory Neural Accelerators
In this work, we show that it is only necessary to select a small portion of the weights for write-verify to maintain the DNN accuracy, thus achieving significant speedup.
RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Search
To the best of the authors' knowledge, this is the first DNAS framework that can handle large search spaces with bounded memory usage.
Uncertainty Modeling of Emerging Device-based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search
Emerging device-based Computing-in-memory (CiM) has been proved to be a promising candidate for high-energy efficiency deep neural network (DNN) computations.
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators
In this paper, we are the first to bring the computing-in-memory architecture, which can easily transcend the memory wall, to interplay with the neural architecture search, aiming to find the most efficient neural architectures with high network accuracy and maximized hardware efficiency.
Optimizing Memory Efficiency for Convolution Kernels on Kepler GPUs
The high computation throughput and memory bandwidth of graphics processing units (GPUs) make GPUs a natural choice for accelerating convolution operations.
