Search Results for author:
Found 40 papers, 8 papers with code
PristiQ: A Co-Design Framework for Preserving Data Security of Quantum Learning in the Cloud
Experimental results on simulation and the actual IBM quantum computer both prove the ability of PristiQ to provide high security for the quantum data while maintaining the model performance in QML.
Edge-InversionNet: Enabling Efficient Inference of InversionNet on Edge Devices
Seismic full waveform inversion (FWI) is a widely used technique in geophysics for inferring subsurface structures from seismic data.
Muffin: A Framework Toward Multi-Dimension AI Fairness by Uniting Off-the-Shelf Models
Model fairness (a. k. a., bias) has become one of the most critical problems in a wide range of AI applications.
A Novel Spatial-Temporal Variational Quantum Circuit to Enable Deep Learning on NISQ Devices
The results of the evaluation on the standard dataset for binary classification show that ST-VQC can achieve over 30% accuracy improvement compared with existing VQCs on actual quantum computers.
QuMoS: A Framework for Preserving Security of Quantum Machine Learning Model
We further developed a reinforcement learning-based security engine, which can automatically optimize the model design under the distributed setting, such that a good trade-off between model performance and security can be made.
On-Device Unsupervised Image Segmentation
What's more, for a larger size image in the BBBC005 dataset, the existing approach cannot be accommodated to Raspberry PI due to out of memory; on the other hand, SegHDC can obtain segmentation results within 3 minutes while achieving a 0. 9587 IoU score.
All-in-One: A Highly Representative DNN Pruning Framework for Edge Devices with Dynamic Power Management
By re-configuring the model to the corresponding pruning ratio for a specific execution frequency (and voltage), we are able to achieve stable inference speed, i. e., keeping the difference in speed performance under various execution frequencies as small as possible.
QuEst: Graph Transformer for Quantum Circuit Reliability Estimation
Specifically, the TorchQuantum library also supports using data-driven ML models to solve problems in quantum system research, such as predicting the impact of quantum noise on circuit fidelity and improving the quantum circuit compilation efficiency.
Towards Real-Time Temporal Graph Learning
Prior work operates on pre-collected temporal graph data and is not designed to handle updates on a graph in real-time.
Towards Sparsification of Graph Neural Networks
In this paper, we utilize two state-of-the-art model compression methods (1) train and prune and (2) sparse training for the sparsification of weight layers in GNNs.
A Length Adaptive Algorithm-Hardware Co-design of Transformer on FPGA Through Sparse Attention and Dynamic Pipelining
Particularly, we develop a hardware-friendly sparse attention operator and a length-aware hardware resource scheduling algorithm.
Quantum Neural Network Compression
Model compression, such as pruning and quantization, has been widely applied to optimize neural networks on resource-limited classical devices.
A Collaboration Strategy in the Mining Pool for Proof-of-Neural-Architecture Consensus
In many recent novel blockchain consensuses, the deep learning training procedure becomes the task for miners to prove their workload, thus the computation power of miners will not purely be spent on the hash puzzle.
The Larger The Fairer? Small Neural Networks Can Achieve Fairness for Edge Devices
Results show that FaHaNa can identify a series of neural networks with higher fairness and accuracy on a dermatology dataset.
Automated Architecture Search for Brain-inspired Hyperdimensional Computing
On the Clintox dataset, which tries to learn features from developed drugs that passed/failed clinical trials for toxicity reasons, the searched HDC architecture obtains the state-of-the-art ROC-AUC scores, which are 0. 80% higher than the manually designed HDC and 9. 75% higher than conventional neural networks.
One Proxy Device Is Enough for Hardware-Aware Neural Architecture Search
A key requirement of efficient hardware-aware NAS is the fast evaluation of inference latencies in order to rank different architectures.
Hardware Aware Neural Architecture Search
Neural Architecture Search
RMSMP: A Novel Deep Neural Network Quantization Framework with Row-wise Mixed Schemes and Multiple Precisions
Specifically, this is the first effort to assign mixed quantization schemes and multiple precisions within layers -- among rows of the DNN weight matrix, for simplified operations in hardware inference, while preserving accuracy.
Detecting Gender Bias in Transformer-based Models: A Case Study on BERT
In this paper, we propose a novel gender bias detection method by utilizing attention map for transformer-based models.
RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Search
To the best of the authors' knowledge, this is the first DNAS framework that can handle large search spaces with bounded memory usage.
Exploration of Quantum Neural Architecture by Mixing Quantum Neuron Designs
Experimental results demonstrate that the identified quantum neural architectures with mixed quantum neurons can achieve 90. 62% of accuracy on the MNIST dataset, compared with 52. 77% and 69. 92% on the VQC and QuantumFlow, respectively.
Can Noise on Qubits Be Learned in Quantum Neural Network? A Case Study on QuantumFlow
Specifically, this paper targets quantum neural network (QNN), and proposes to learn the errors in the training phase, so that the identified QNN model can be resilient to noise.
A Compression-Compilation Framework for On-mobile Real-time BERT Applications
In this paper, we propose a compression-compilation co-design framework that can guarantee the identified model to meet both resource and real-time specifications of mobile devices.
Dancing along Battery: Enabling Transformer with Run-time Reconfigurability on Mobile Devices
Specifically, RT3 integrates two-level optimizations: First, it utilizes an efficient BP as the first-step compression for resource-constrained mobile devices; then, RT3 heuristically generates a shrunken search space based on the first level optimization and searches multiple pattern sets with diverse sparsity for PP via reinforcement learning to support lightweight software reconfiguration, which corresponds to available frequency levels of DVFS (i. e., hardware reconfiguration).
On the Universal Approximability and Complexity Bounds of Deep Learning in Hybrid Quantum-Classical Computing
With the continuously increasing number of quantum bits in quantum computers, there are growing interests in exploring applications that can harvest the power of them.
FGNAS: FPGA-Aware Graph Neural Architecture Search
The success of gragh neural networks (GNNs) in the past years has aroused grow-ing interest and effort in designing best models to handle graph-structured data.
When Machine Learning Meets Quantum Computers: A Case Study
It is imminent to know how to design the quantum circuit for accelerating neural networks.
DNA: Differentiable Network-Accelerator Co-Search
Powerful yet complex deep neural networks (DNNs) have fueled a booming demand for efficient DNN solutions to bring DNN-powered intelligence into numerous applications.
MSP: An FPGA-Specific Mixed-Scheme, Multi-Precision Deep Neural Network Quantization Framework
To tackle the limited computing and storage resources in edge devices, model compression techniques have been widely used to trim deep neural network (DNN) models for on-device inference execution.
Real-Time Execution of Large-scale Language Models on Mobile
Our framework can guarantee the identified model to meet both resource and real-time specifications of mobile devices, thus achieving real-time execution of large transformer-based models like BERT variants.
Towards Cardiac Intervention Assistance: Hardware-aware Neural Architecture Exploration for Real-Time 3D Cardiac Cine MRI Segmentation
Experimental results on ACDC MICCAI 2017 dataset demonstrate that our hardware-aware multi-scale NAS framework can reduce the latency by up to 3. 5 times and satisfy the real-time constraints, while still achieving competitive segmentation accuracy, compared with the state-of-the-art NAS segmentation framework.
Standing on the Shoulders of Giants: Hardware and Neural Architecture Co-Search with Hot Start
To tackle this issue, HotNAS builds a chain of tools to design hardware to support compression, based on which a global optimizer is developed to automatically co-search all the involved search spaces.
BUNET: Blind Medical Image Segmentation Based on Secure UNET
The strict security requirements placed on medical records by various privacy regulations become major obstacles in the age of big data.
MS-NAS: Multi-Scale Neural Architecture Search for Medical Image Segmentation
The recent breakthroughs of Neural Architecture Search (NAS) have motivated various applications in medical image segmentation.
A Co-Design Framework of Neural Networks and Quantum Circuits Towards Quantum Advantage
We discover that, in order to make full use of the strength of quantum representation, it is best to represent data in a neural network as either random variables or numbers in unitary matrices, such that they can be directly operated by the basic quantum logical gates.
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks
Neural Architecture Search (NAS) has demonstrated its power on various AI accelerating platforms such as Field Programmable Gate Arrays (FPGAs) and Graphic Processing Units (GPUs).
NASS: Optimizing Secure Inference via Neural Architecture Search
Due to increasing privacy concerns, neural network (NN) based secure inference (SI) schemes that simultaneously hide the client inputs and server models attract major research interests.
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators
In this paper, we are the first to bring the computing-in-memory architecture, which can easily transcend the memory wall, to interplay with the neural architecture search, aiming to find the most efficient neural architectures with high network accuracy and maximized hardware efficiency.
On Neural Architecture Search for Resource-Constrained Hardware Platforms
With 30, 000 LUTs, a light-weight design is found to achieve 82. 98\% accuracy and 1293 images/second throughput, compared to which, under the same constraints, the traditional method even fails to find a valid solution.
Hardware/Software Co-Exploration of Neural Architectures
We propose a novel hardware and software co-exploration framework for efficient neural architecture search (NAS).
Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search
In addition, with a performance abstraction model to analyze the latency of neural architectures without training, our framework can quickly prune architectures that do not satisfy the specification, leading to higher efficiency.
